1386660 cgoxopx 1589041069
5
FPGA神经网络
2116178 lvcs 1578966555
4
Digital-Logic-Experiment
2116178 lvcs 1578966555
3
西安交通大学FPGA专题实验 数字钟和出租车计价器
VHDL
1 year ago
5440949 yuanbo peng 1578986769
0
This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.
VHDL
1 year ago
0
VHDL
7 months ago

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