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Apache-2.0

riscv-fpga-toolchain

介绍

Tinyriscv简单易读,原作者文档优秀,这里将tinyriscv移植到基于国产FPGA(安陆EG4S20)的开发板荔枝唐上。此编译链将整合RISCV编译链,windows x86 TCC编译器(win侧工具开发),iverilog仿真环境,等等。此编译链仅支持windows。

Tinyriscv: https://gitee.com/liangkangnan/tinyriscv

anlogic荔枝tang介绍及资源:https://wiki.sipeed.com/hardware/tang/zh/

anlogic荔枝tang Guide:http://tang.lichee.pro/

tcc相关:https://bellard.org/tcc/

iverilog/GTKwave win版本下载:http://bleyer.org/icarus/

tinyriscv资源在荔枝tang上最高能跑48M(高于48M,core运行code有问题,但是jtag能够正常访问ram和外设)。消耗如下

avatar avatar

在TD开发环境下整个RTL编译时间大概在8分钟内。

目录结构

sdk 存放tinyriscv sdk环境。

fpga 目录存放对应verilog代码,TD工程,以及仿真代码和脚本。sim目录存在仿真代码,test目录存放对应测试c代码,tb目录verilog测试脚本(与tinyriscv保持一致)

tools 目录存放工具和编译链。

硬件依赖

  1. 荔枝tang FPGA开发板。 avatar

  2. cmsis-dap仿真器(下图dap自带usb转串口)或者jlink仿真器(jlink不管v9还是v10无法直接jlink command或者ozone进行RV调试,需要将jlink配置为openocd可调用的方式可以参考此文章进行配置https://blog.csdn.net/qingwufeiyang12346/article/details/45954595) avatar

  3. USB转串口(调试串口)。

软件依赖

  1. 编译FPGA工程需要安装TD开发环境,如果需要运行脚本编译,需要将安装路径添加到全局PATH变量(安装过程中会提示)。
  2. 如果需要仿真,需要安装iverilog,并添加安装路径到全局PATH变量.

使用说明

FPGA编译说明
  1. 直接到fpga目录打开prove.al用TD IDE进行fpga编译
  2. 运行cmd.bat,打开命令行窗口。运行fpga_compile.bat脚本编译,此脚本调用fpga/compile.tcl进行编译。
SDK编译说明

运行cmd.bat,打开命令行窗口。运行sdk.bat脚本进行库编译,编译完成后再运行make test编译test工程,编译完成会在根目录下新建out目录,且输出elf,bin,dump等文件到out目录对应文件夹

仿真说明
  1. 运行cmd.bat,打开命令行窗口,进入fpga/sim目录,如需单独编译可以运行compile_rtl.py ..命令触发iverilog编译rtl。(注:默认打开了PLL编译无法通过,需要去掉PLL相关代码进行仿真,如下图所示部分需要修改clk相关代码 ) avatar

  2. 运行sim_new_nowave.py ..\tests\example\simple\simple.bin inst.data生成inst.data文件( 需先进入tests\example\simple目录运行make进行编译 ),并且触发编译。

  3. 运行fpga/sim目录下sim.bat,会自动打开gtkwave工具查看仿真波形。如下图所示 avatar

调试说明
  1. 使用TD IDE或者脚本将生成的bit文件下载到目标板

  2. 运行cmd.bat,打开命令行窗口,运行openocd.bat脚本,此脚本会调用openocd使用tinyriscv_jlink.cfg( 如使用cmsis-dap需要修改为tinyriscv_cmsisdap.cfg ),运行正常显示如下图 avatar

  3. 运行putty.bat脚本,选择telnet,如下图配置 avatar

  4. putty界面下输入指令进行调试。附openocd常用调试指令如下

halt	-暂停CPU
reset	-复位目标板
resume 	-恢复运行
resume 0x123456   -从0x123456地址恢复运行
reg <register>    -打印register寄存器的值

load_image <File Name> <Addr>	   -烧写二进制文件到指定地址
例: load_image image.bin 0x4000000 -烧写image.bin到0x4000000

将内存从地址Addr开始的Size字节数据读出,保存到文件File Name中
dump_image <File Name> <Addr> <Size> 

将文件File Name与内存Addr开始的数据进行比较,格式可选,bin、ihex、elf
verify_image <File Name> <Addr> [bin|ihex|elf] 	

step [Addr]	-不加地址:从当前位置单步执行; 加地址:从Addr处单步执行
poll		-查询目标板当前状态
bp <Addr> <Length> [hw] -在Addr地址设置断点,指令长度为Length,hw代表硬件断点
rbp <Addr>		 -删除Addr处的断点

mdw <Addr> [Count]  -显示从物理地址Addr开始的Count(缺省则默认为1)个字(4Bytes)
mdh <Addr> [Count]  -显示从物理地址Addr开始的Count(缺省则默认为1)个半字(2Bytes)
mdb <Addr> [Count]  -显示从物理地址Addr开始的Count(缺省则默认为1)个字节(1Byte)
mww <Addr> <Value>  -向物理地址Addr写入Value,大小:一个字(4Bytes)
mwh <Addr> <Value>  -向物理地址Addr写入Value,大小:一个半字(2Bytes)
mwb <Addr> <Value>  -向物理地址Addr写入Value,大小:一个字节(1Bytes)
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简介

Tinyriscv简单易读,原作者文档优秀,这里将tinyriscv移植到基于国产FPGA(安陆EG4S20)的开发板荔枝唐上。此编译链将整合RISCV编译链,x86 TCC编译器(win侧工具开发),iverilog仿真环境,等等。 后续增加vexriscv,及SpinalHDL相应环境。 展开 收起
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