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Drinkto / zhangz-project

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verilogNote.md 676 Bytes
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Drinkto 提交于 2023-01-25 03:21 . Update Project files

verilator --cc --exe --build -j 0 -Wall sim_main.cpp our.v

  1. --cc to get C++ output (versus e.g., SystemC, or only linting).

  2. --exe, along with our sim_main.cpp wrapper file, so the build will create an executable instead of only a library.

  3. --build so Verilator will call make itself. This is we don’t need to manually call make as a separate step. You can also write your own compile rules, and run make yourself as we show in Example SystemC Execution.)

  4. -j 0 to Verilate using use as many CPU threads as the machine has.

  5. -Wall so Verilator has stronger lint warnings enabled.

  6. And finally, our.v which is our SystemVerilog design file.

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