Zhou Fan (范舟)
This project is a RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, which is a course project of Computer Architecture, ACM Class @ SJTU.
Feature | RISC-V CPU |
---|---|
ISA | RISC-V (RV32I subset) |
Pipelining | 5 stages |
Data forwarding | √ |
Cache | N-way set associate I-cache and D-cache [1] |
UART module | passed simulation [2] |
Security | perfect proof against Meltdown and Spectre attack [3] |
This CPU project has a five stage pipeline with data forwarding. In the picture below, red paths show stall control flow, while orange ones show data forwarding path.
For program test on FPGA without capable memory, this CPU uses UART protocol to communicate with PC, where runs a memory simulator.
This CPU is simulated with UART communication module in Xilinx vivado.
Implementation on Basys3 FPGA, using Xilinx vivado. Scematic Overview CPU Module Scematic
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